The present invention relates to data reproducing technology, and more particularly, to a data reproducing controller for controlling a data reproducing device that reproduces data, which is recorded on a recording medium and to which an error correction code is added.
Generally, when recording data on a recording medium, an error detection code (EDC) and an error correction code are added to the data to reproduce the data with high reliability.
For example, a DVD recording device, which uses a digital versatile disc (DVD) as a recording medium, records data as described below.
Referring to FIG. 1, the data subject to recording (main data) is divided into units of 2048 bytes. A header consisting of 12 bytes is added to the head of each piece of main data. An error detection code (EDC) consisting of 4 bytes is added to the end of each piece of main data. This configures segments of sector data having 2064 bytes. Each data sector is configured by 12 rows with each row having 172 bytes.
The sector data is scrambled to generate scrambled data. Referring to FIG. 2, 16 rows of an outer code parity (PO) and 10 columns of an inner code parity (PI) are added to 16 pieces of successive scrambled data (i.e., 172 bytes×192 rows) to generate an error check and correction (ECC) block. The ECC block has 208 rows with each row having 182 bytes (182 bytes×208 rows).
The PI added to each row is generated based on the 172 bytes of data included in the row. Further, the PO added to each column is generated based on the 192 bytes of data included in the column.
The ECC block is further converted as shown in FIG. 3. More specifically, each of the 16 rows of the PO are shifted to a position following one of the 16 pieces of sector data so that one row of the PO is arranged subsequent to each piece of sector data to which the PI is added. A recording sector is configured from 13 rows of data with each row having 182 bytes. The 13 rows of the recording sector includes 12 rows, each having 172 bytes, 12 rows of the PI, each having 10 bytes, and 1 row of the PO having 182 bytes.
The recording sector is modulated to generate recording data. The recording data is converted to serial data and written to a DVD.
The reproduction of the recording data to which the error correction code is added will now be discussed with reference to FIG. 4. In FIG. 4, a data reproducing controller 100, which controls the reproduction of data, is illustrated in the broken line.
An RF amplifier 112 amplifies a signal, which is detected by a pickup 111, and provided to a read channel circuit 113. In response to the signal, the read channel circuit 113 generates a binary signal and samples the binary signal in accordance with a read channel clock signal, which has a predetermined frequency. A synchronization detection circuit 114 detects a synchronizing signal from the sampled signal and extracts data from the sampled signal based on the synchronizing signal. A demodulation circuit 115 demodulates the extracted data and provides the demodulated data to a buffering circuit 116. Whenever a predetermined amount of the demodulated data is accumulated, the buffering circuit 116 writes the accumulated demodulated data to a buffer memory 118, which is configured by a dynamic random access memory (DRAM), via a memory access circuit 117.
When the amount of data written to the buffer memory 118 reaches one ECC block or more, a PI correction circuit 121 sends a request to the buffer memory 118 for reading part of the data in the buffer memory 118 that requires error correction. In response to the data read request, the buffer memory 118 sequentially provides the requested data to a first in first out (FIFO) 122 via the memory access circuit 117. When one row of an ECC block, or 182 bytes of data, is accumulated in the FIFO 122, the PI correction circuit 121 reads the data from the FIFO 122 and performs an error correction process on an error correction code (PI), which is included in the row of data. The PI correction circuit 121 provides the data that has undergone error correction to a descrambling circuit 123. The descrambling circuit 123 descrambles the data and provides the data to an FIFO 124. Whenever a row of data is accumulated, the FIFO 124 writes the data to the buffer memory 118 via the memory access circuit 117. In this manner, the buffer memory 118 stores the data that has undergone the error correction.
An error detection circuit 125 performs error detection on the data of the PI that has undergone the error correction process. The error detection result is held in the error detection circuit 125 for a predetermined period to enable an external circuit to refer to the result.
From the data stored in the buffer memory 118, a scrambling circuit 127 reads and scrambles the data that has been descrambled by the descrambling circuit 123. A PO correction circuit 128 performs error correction on the PO in the data that has undergone scrambling and provides the corrected data to the descrambling circuit 123. The descrambling circuit 123 descrambles the received data and writes the descrambled data to the buffer memory 118 via the FIFO 124 and the memory access circuit 117.
In addition to the access via the memory access circuit 117, the buffer memory 118 is accessed by other circuits and devices, such as a microcomputer (not shown). As the frequency in which the buffer memory 118 is accessed increases, the time for waiting to access the buffer memory 118 increases. The lengthened wait time increases the time required to perform the above series of processes, which control data reproduction, and the time required to access the buffer memory 118 with other devices. Thus, it is difficult to increase the speed for reproducing the recording data from the DVD.